The present invention relates to electronic ballasts and, more particularly, to electronic dimming ballasts for gas discharge lamps, such as fluorescent lamps.
Electronic ballasts for fluorescent lamps typically can be analyzed as comprising a “front end” and a “back end”. The front end typically includes a rectifier for changing alternating current (AC) mains line voltage to a direct current (DC) bus voltage and a filter circuit for filtering the DC bus voltage. Electronic ballasts also often use a boost circuit for boosting the magnitude of the DC bus voltage. The filter circuit typically comprises a capacitive low-pass filter.
The ballast back end typically includes a switching inverter for converting the DC bus voltage to a high-frequency AC voltage, and a resonant tank circuit having a relatively high output impedance for coupling the high-frequency AC voltage to the lamp electrodes. The ballast back end also typically includes a feedback circuit that monitors the lamp current and generates control signals to control the switching of the inverter so as to maintain a desired lamp current magnitude.
In order to maintain stable lamp operation, typical prior art electronic ballasts filter the DC bus voltage to minimize the amount of bus voltage ripple. This is usually accomplished by providing a bus capacitor having a relatively large capacitance and hence, a relatively large energy storage capacity. By providing a relatively large bus capacitor, the amount of decay from the rectified peak voltage is minimized from one half-cycle to the next half-cycle. Minimizing the amount of ripple on the DC bus also tends to minimize the current crest factor (CCF) of the lamp current. The CCF is defined as the ratio of the magnitude of the peak lamp current to the magnitude of the root-mean-square (RMS) value of the lamp current.(Equation 1)
                    CCF        ≡                              I            pk                                I            RMS                                              (                  Equation          ⁢                                          ⁢          1                )            
However, using a relatively large bus capacitor to minimize ripple on the DC bus voltage comes with its disadvantages. The bus capacitor must be fairly large, and is therefore more expensive and consumes more area on a printed circuit board, or the like, and volume within the ballast. Also, because the bus capacitor is discharging whenever the bus voltage level is above the absolute value of the AC mains voltage, the bus capacitor is recharging during a relatively short duration of each line half-cycle centered about the peak of the line voltage. This results in the typical prior art ballast having a tendency to draw a relatively large amount of current during the time that the bus capacitor is charging, as shown in FIG. 1. Consequently, this results in a distorted input current waveform giving rise to unwanted harmonics and undesirable total harmonic distortion (THD) and power factor for the ballast.
One approach to lowering the THD and improving the ballast power factor has been to employ an active power factor correction (APFC) circuit. This approach has resulted in tradeoffs. Using an APFC circuit results in added ballast complexity, more components, greater cost, lower reliability, and possibly increased power consumption. Moreover, the ballast typically uses a relatively large bus capacitor with its attendant disadvantages as noted above.
Another approach to lowering THD and improving ballast power factor has been to employ a valley-fill circuit between a rectifier and an inverter. One disadvantage of typical prior art valley-fill circuits is that they can have greater bus ripple, which results in higher lamp CCF, which can in turn shorten lamp life.
Prior art approaches to providing electronic ballasts having improved power factor are and THD are discussed in T.-F. Wu, Y.-J. Wu, C.-H. Chang and Z.-R. Liu, “Ripple-Free, Single-Stage Electronic Ballasts with Dither-Booster Power Factor Corrector”, IEEE Industry Applications Society Annual Meeting, pp. 2372-77, 1997; Y.-S. Youn, G. Chae, and G.-H. Cho, “A Unity Power Factor Electronic Ballast for Fluorescent Lamp having Improved Valley Fill and Valley Boost Converter”, IEEE PESC97 Record, pp. 53-59, 1997; and G. Chae, Y.-S. Youn, and G.-H. Cho, “High Power Factor Correction Circuit using Valley Charge-Pumping for Low Cost Electronic Ballasts”, IEEE 0-7803-4489-8/98, pp. 2003-8, 1998.
Prior art patents representative of attempts to provide electronic ballasts having improved power factor and THD include U.S. Pat. No. 5,387,847, “Passive Power Factor Ballast Circuit for the Gas Discharge Lamps”, issued Feb. 7, 1995 to Wood; U.S. Pat. No. 5,399,944, “Ballast Circuit for Driving Gas Discharge”, issued Mar. 21, 1995 to Konopka et al.; U.S. Pat. No. 5,517,086, “Modified Valley Fill High Power Factor Correction Ballast”, issued May 14, 1996 to El-Hamamsy et al.; and U.S. Pat. No. 5,994,847, “Electronic Ballast with Lamp Current Valley-Fill Power Factor Correction”, issued Nov. 30, 1999.